Method of forming a pattern in a semiconductor device and method of forming a gate using the same

ABSTRACT

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

CROSS-REFERENCE OF RELATED APPLICATIONS

This application relies for priority upon Korean Patent Application No.2003-97427 filed on Dec. 26, 2003, the contents of which are hereinincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a pattern for asemiconductor device. More particularly, the present invention relatesto a method of forming a pattern of which line width is much smaller andfiner in a cell region than in a peripheral region of a semiconductordevice.

2. Description of the Related Art

Forming a fine circuit on a semiconductor substrate includes an impurityimplantation, a patterning process and an electrical connection betweenseparated portions. Impurities are implanted on a small surface portionof a silicon substrate in a precise amount, and then a sacrificial layeris formed on the substrate including the impurities. Then, thesacrificial layer is patterned in accordance with a mask pattern, andthe substrate or a thin layer on the substrate is partially removedusing the sacrificial layer pattern as a mask, so that the substrate orthe thin layer thereon has a pattern of separated portions. Finally, theseparated portions of the substrate or the thin layer are electricallyconnected with each other, thereby forming a semiconductor deviceincluding an integrated circuit such as a very large scale integration(VLSI) chip. Here, a photolithography process, in general, is performedfor defining the implantation region or forming the pattern.

According to the photolithography process, a photoresist material thatis very sensitive to light is coated on the semiconductor substrate or awafer, thereby forming a photoresist film on the wafer. The light suchas an ultraviolet ray, an electron beam or an X-ray is irradiated ontothe photoresist film through a mask or a reticle. Then, the photoresistfilm is selectively exposed to the light and developed through apredetermined process, thus finally a photoresist pattern is formed inaccordance with or contrary to a mask pattern, which is referred to as apositive pattern or a negative pattern. In a subsequent process, while aportion of the substrate or a thin layer thereon covered by thephotoresist pattern is protected from the process, the other portion ofthe substrate or the thin layer thereon exposed through the photoresistpattern is subjected to the process.

When the photoresist pattern is used as an etching mask, a portion ofthe thin layer exposed through the photoresist pattern is partiallyetched away, thus the thin layer on the substrate is formed into apredetermined pattern in accordance with the photoresist pattern.

The above photolithography process has certain drawbacks. Firstly, whenthe photoresist film is exposed to the light, an exposure condition maybe minutely different from each point in a shot, so that a line width isvaried throughout chips on the wafer.

Secondly, when the photoresist film is exposed to the light, an exposurecondition of every shot may be minutely different from each other, sothat a critical dimension (CD) of the chip is varied in accordance witha region of the wafer.

Thirdly, when an etching process is performed using the photoresistpattern as a mask, an edge line of an etched portion of the thin layerbecomes very rough since the photoresist pattern becomes non-uniform,which is referred to as a line edge roughness phenomenon.

Due to the above-mentioned problems, a line width distribution of thepatterns in each unit cell in a chip has a substantial effect onperformance of the highly-integrated memory device such as the VLSIchip. Non-uniformity of the line width distribution causes electricalcharacteristics of each unit device in a chip or in a wafer to benon-uniform, thus causing various process failures in the semiconductordevice. In addition, a non-uniform etching of the photoresist filmdegrades a short channel characteristic of the device, and a gate sizereduction accelerates the degradation of the short channelcharacteristic of the device.

Accordingly, a manufacturing process for a high-integrated semiconductordevice has required a new method of forming a pattern with more accuracyand fineness than by the photolithography process.

For example, Japanese Publication Patent No. 2002-280388 discloses amethod of forming a line and space pattern having a minute pitch smallerthan a resolution of the exposing process. In detail, a secondinsulating layer is formed on a sidewall of a first insulating layerpattern, and then the first insulating layer pattern is removed. Anetching process is performed using the second insulating layer as anetching mask, thereby forming a pattern. However, when the secondinsulating layer is used as an etching mask, the pattern has the sameline width across a whole surface of a substrate, and as a result, thepattern may not have a line width greater than that of the secondinsulating layer at any local area on the substrate. In addition, sincethe second insulating layer is shaped in accordance with the shape ofthe sidewall of the first insulating layer, various patterns may not beformed when the second insulating layer is used as an etching mask.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a method of forming a minutepattern having various line widths at different regions of asemiconductor substrate.

The present invention also provides a method of forming a gate patternhaving various line widths at different regions of a semiconductorsubstrate.

According to one aspect of the present invention, there is provided amethod of forming a pattern of a semiconductor device. A semiconductorsubstrate on which an object layer to be patterned is formed isprovided, and the substrate is divided into a cell region and aperipheral region. A buffer layer is formed on the object layer, and thebuffer layer is partially etched away from the object layer by aphotolithography process. Therefore, the buffer layer in the cell regionof the substrate is formed into a buffer pattern, and the buffer layerin the peripheral region of the substrate is completely removed. A hardmask layer is formed on the buffer pattern in the cell region and theobject layer in the peripheral region. The hard mask layer isanisotropically and selectively etched away only in the cell region ofthe substrate, so that a spacer is formed along a sidewall of the bufferpattern in the cell region, and the hard mask layer still remains on theobject layer in the peripheral region of the substrate. Then, the bufferpattern is removed from the object layer, so that only the spacerremains on the object layer along a first direction. The spacer ispartially removed in a second direction different from the firstdirection and the hard mask layer is simultaneously removed, so that thespacer is separated along the second direction, thereby forming a cellhard mask pattern in the cell region and a peripheral hard mask patternis formed in the peripheral region. The object layer is partially etchedaway using the cell hard mask pattern and the peripheral hard maskpattern as an etching mask.

The cell region of the substrate includes a plurality of unit memorydevices, and a plurality of patterns having the same line widths isrepeatedly formed in the cell region. The peripheral region of thesubstrate includes a plurality of peripheral circuits for driving theunit memory device, and each line width of the pattern can be differentfrom the others. In addition, the line width of the pattern in theperipheral region is relatively greater as compared with that of thepattern in the cell region. In one embodiment, a width of the spacer isless than a critical dimension (CD) of a photolithography process. Inone embodiment, the buffer layer comprises a material having an etchingselectivity with respect to the hard mask layer. The hard mask layer cancomprise a material having an etching selectivity with respect to boththe object layer and the buffer layer. Examples of the buffer layerinclude a silicon oxide layer or a polysilicon layer. In case that theobject layer comprises the same material as the buffer layer, aseparation layer is further formed between the object layer and thebuffer layer for separating the object layer from the buffer layer. Theseparation layer comprises a material having an etching selectivity withrespect to the object layer. In one embodiment, the hard mask layercomprises a silicon oxynitride layer or a silicon oxide layer. Theobject layer can include a gate electrode layer, a silicon substrate ina field region or a metal layer for forming a metal wiring. In moredetail, the object layer includes a cell gate, active/field pattern or ametal wiring of an I-type SRAM device having a straight active pattern.In one embodiment, a width of the spacer is less than a criticaldimension (CD) of a photolithography process. A line width of theperipheral hard mask pattern is greater than that of the cell hard maskpattern.

Since the cell hard mask pattern is formed on sidewalls of the bufferpattern, a pair of patterns is repeatedly formed at regular intervals inthe cell region. That is, the present invention may be applied to amethod of manufacturing the semiconductor device in which a pair ofpatterns is repeated at regular intervals in the cell region. Inaddition, since the peripheral hard mask pattern is always formedwithout a limitation in its shape, the minute pattern in the peripheralregion is readily formed in accordance with various design conditions.

According to another aspect of the present invention, there is providedanother method of forming a pattern of a semiconductor device. Asemiconductor substrate is provided. An object layer to be patterned isformed on the substrate, and the substrate is divided into a cell regionand a peripheral region. A buffer layer is formed on the object layer,and the buffer layer is partially etched away from the object layer by aphotolithography process such that the buffer layer in the cell regionof the substrate is formed into a buffer pattern, and the buffer layerin the peripheral region of the substrate is removed. A spacer is formedalong a sidewall of the buffer pattern, and the buffer pattern isremoved from the object layer, so that only the spacer remains on theobject layer along a first direction. A hard mask layer is formed on theobject layer including the spacer extending along the first direction.The hard mask layer and the spacer are at least partially removed in asecond direction different from the first direction in the cell regionof the substrate, so that the spacer and the hard mask layer on thespacer are separated from each other along the second direction in thecell region. The hard mask layer is at least partially removed such thatthe hard mask layer on the spacer is removed in the cell region and thehard mask layer on the object layer is at least partially removed in theperipheral region, thereby forming a cell hard mask pattern in the cellregion and a peripheral hard mask pattern in the peripheral region. Theobject layer is at least partially removed by etching using the cellhard mask pattern and the peripheral hard mask pattern as an etchingmask. In one embodiment, a width of the spacer is less than a criticaldimension (CD) of a photolithography process. The buffer layer cancomprise a material having an etching selectivity with respect to thehard mask layer. The method can further comprise, in the case in whichthe object layer comprises the same material as the buffer layer,forming a separation layer between the object layer and the buffer layerfor separating the object layer from the buffer layer, the separationlayer comprising a material having a high etching selectivity withrespet to the object layer. The spacer and the hard mask layer cancomprise a material having a high etching selectivity with respect tothe object layer and the buffer layer. In one embodiment, the hard masklayer is the same material as the spacer. The hard mask layer cancomprise a silicon oxynitride layer or a silicon oxide layer. The objectlayer can include a gate electrode layer, a silicon substrate in a fieldregion or a metal layer for forming a metal wiring.

Therefore, the pattern in the wafer may have a different line widthaccording to the region of the wafer, and the line width may be lessthan the CD of the photolithography process. In addition, the line widthvariation due to the photolithography process may be minimized. Further,since the hard mask layer is uniformly etched away, line edge roughnessdue to a non-uniform etching may also be minimized.

According to another aspect of the present invention, there is provideda method of forming a gate in a semiconductor device. A gate oxide layerand a gate electrode layer are formed on a substrate, and the substrateis divided into a cell region and a peripheral region. A buffer layer isformed on the gate electrode layer, and the buffer layer is at leastpartially etched from the gate electrode layer by a photolithographyprocess such that the buffer layer in the cell region of the substrateis formed into a buffer pattern, and the buffer layer in the peripheralregion of the substrate is removed. A hard mask layer is formed on thebuffer pattern in the cell region of the substrate and the gateelectrode layer in the peripheral region of the substrate. The hard masklayer is selectively etched away only in the cell region of thesubstrate anisotropically, so that a spacer is formed along a sidewallof the buffer pattern in the cell region, and the hard mask layer stillremains on the gate electrode layer in the peripheral region of thesubstrate. The buffer pattern is removed from the gate electrode layer,so that only the spacer remains on the gate electrode layer along afirst direction. The spacer is at least partially removed in a seconddirection different from the first direction and the hard mask layer, sothat the spacer is separated along the second direction, thereby forminga cell hard mask pattern in the cell region and a peripheral hard maskpattern in the peripheral region. The gate electrode layer is at leastpartially etched using the cell hard mask pattern and the peripheralhard mask pattern as an etching mask.

In one embodiment, the gate electrode layer comprises polysilicon.

The buffer layer can include a silicon oixde layer or a polysiliocnlayer.

In one embodiment, the method includes, in case that the buffer layerincludes the polysilicon layer, forming a separation layer between thegate electrode layer and the buffer layer for separating the gateelectrode layer from the buffer layer, the separation layer comprising amaterial having a high etching selectivity with respect to polysilicon.

The hard mask layer can comprise a silicon oxynitride layer or a siliconoxide layer.

According to still another aspect of the present invention, there isprovided a method of forming a gate in a semiconductor device. A gateoxide layer and a gate conductive layer are formed on a substrate thatis divided into a cell region and a peripheral region. A buffer layer isformed on the gate conductive layer, and the buffer layer is at leastpartially etched from the gate conductive layer by a photolithographyprocess such that the buffer layer in the cell region of the substrateis formed into a buffer pattern, and the buffer layer in the peripheralregion of the substrate is removed. A spacer is formed on a sidewall ofthe buffer pattern, and the buffer pattern is removed from the gateconductive layer, so that only the spacer remains on the gate conductivelayer along a first direction. A hard mask layer is formed on the gateconductive layer including the spacer extending along the firstdirection. The hard mask layer and the spacer are at least partiallyetched away in a second direction different from the first direction inthe cell region of the substrate, so that the spacer and the hard masklayer on the spacer are separated from each other along the seconddirection in the cell region. The hard mask layer is at least partiallyetched away such that the hard mask layer on the spacer is removed inthe cell region of the substrate and the hard mask layer on the gateconductive layer is at least partially removed in the peripheral regionof the substrate, thereby forming a cell hard mask pattern in the cellregion of the substrate and a peripheral hard mask pattern in theperipheral region of the substrate. The gate conductive layer is atleast partially etched away using the cell hard mask pattern and theperipheral hard mask pattern as an etching mask.

Therefore, the gate pattern formed to have a smaller line width in thecell region than in the peripheral region. In addition, the line widthvariation and the line edge roughness due to the photolithographyprocess may be minimized.

In one embodiment, the gate electrode layer comprises polysilicon.

The buffer layer can include a silicon oxide layer or a polysiliconlayer.

In one embodiment, the method further comprises, in case that the bufferlayer comprises polysilicon, forming a separation layer between the gateconductive layer and the buffer layer for separating the gate conductivelayer from the buffer layer, the separation layer comprising a materialhaving an etching selectivity with respect to the polysilicon.

In one embodiment, the hard mask layer includes a silicon oxynitridelayer or a silicon oxide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of the invention will beapparent from the more particular description of an embodiment of theinvention, as illustrated in the accompanying drawing. The drawing isnot necessarily to scale, emphasis instead being placed uponillustrating the principles of the invention. Like reference charactersrefer to like elements throughout the drawings.

FIG. 1 is a plan view illustrating a semiconductor substrate that isdivided into a cell region and a peripheral region.

FIGS. 2A, 3A, 4A, 5A, 6A, 7A and 8A are plan views showing processingsteps of a method of forming a pattern of an I-type static random accessmemory (SRAM) device according to a first embodiment of the presentinvention.

FIGS. 2B, 3B, 4B, 5B, 6B, 7B and 8B are cross-sectional views takenalong line I-I′ of FIGS. 2A, 3A, 4A, 5A, 6A, 7A and 8A, respectively.

FIGS. 9A and 10A are plan views showing processing steps of a method offorming a pattern of an I-type SRAM device according to a secondembodiment of the present invention.

FIGS. 9B and 10B are cross-sectional views taken along line I-I′ ofFIGS. 9A and 10A, respectively.

FIG. 11 is a cross-sectional view taken along line I-I′ of the planviews of FIGS. 9A and 10A, showing additional process steps in themethod of FIGS. 9A, 9B, 10A and 10B.

FIGS. 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A and 20A are plan viewsshowing processing steps of a method of forming a gate of an I-typestatic random access memory (SRAM) device according to a thirdembodiment of the present invention.

FIGS. 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B and 20B are cross-sectionalviews taken along line I-I′ of FIGS. 12A, 13A, 14A, 15A, 16A, 17A, 18A,19A and 20A, respectively.

DESCRIPTION OF THE EMBODIMENTS Embodiment 1

FIG. 1 is a plan view illustrating a semiconductor substrate that isdivided into a cell region and a peripheral region. FIGS. 2A through 8Bare plan views and cross sectional views showing processing steps of amethod of forming a pattern of an I-type static random access memory(SRAM) device according to a first embodiment of the present invention.Throughout FIGS. 2A through 8B, each capital letter A designates a planview illustrating the I-type SRAM device, and each capital letter Bdesignates a cross sectional view taken along the line I-I′ of thecorresponding figure designated by the capital letter A.

Referring to FIG. 1, a semiconductor substrate including a cell regionand a peripheral region is provided. A unit memory device is positionedin the cell region, and a driving circuit for driving the unit memorydevice is positioned in the peripheral region. A plurality of N typeimpurities is selectively supplied to surface portions of the siliconsubstrate at which a P type metal-oxide semiconductor (PMOS) transistoris to be formed, thereby forming an N well. A conventional deviceisolation process is performed on the substrate including the N well,thus a plurality of active regions is defined in accordance with aplurality of field regions.

In detail, as an exemplary embodiment, a pad oxide layer, a siliconnitride layer and an anti-reflection layer (ARL) are formed on thesubstrate. The ARL comprises, for example, silicon oxynitride (SiON). Afirst photoresist film is coated on the silicon nitride layer, and anexposing process is performed on the first photoresist film using apredetermined exposure mask, thereby forming a first photoresistpattern.

Then, the ARL and the silicon nitride layer are partially etched usingthe first photoresist pattern as an etching mask, thereby forming asilicon nitride layer pattern and an ARL pattern, respectively. The padoxide layer and the silicon substrate are partially etched using thesilicon nitride layer pattern and an ARL pattern as a hard mask, thus atrench corresponding to the field region is formed on the substrate. TheARL pattern is removed during the etching process and a cleaning processsubsequent to the etching process. The silicon oxide layer is coated onthe silicon nitride pattern to a predetermined thickness such that thetrench is filled with the silicon oxide layer. Then, the silicon oxidelayer is polished until the silicon nitride layer pattern is exposed,thereby forming the field oxide layer 12.

The silicon nitride layer and the pad oxide layer are removed, and theactive region is defined in accordance with the field region. As shownin FIG. 1, the active pattern 11 is formed to be a parallel line shape.

Referring to FIGS. 2A and 2B, a gate oxide layer 14 is formed on thesubstrate 10 including the line shaped active pattern 11 to a thicknessof about 10 Å to about 300 Å. A polysilicon layer 16 is formed on thegate oxide layer 14 as a gate electrode layer. A metal silicide layer(not shown) may be further formed on the polysilicon layer 16.

A buffer layer 18 is formed on the polysilicon layer 16. The bufferlayer 18 comprises a material having an etching selectivity with respectto the polysilicon layer, such as silicon oxide. A thickness of a cellhard mask pattern for patterning the polysilicon layer is determined inaccordance with a thickness of the buffer layer 18.

A second photoresist film is coated on the buffer layer 18, and thesecond photoresist film in the cell region is partially removed, and thesecond photoresist film in the peripheral region is completely removed.Therefore, a second photoresist pattern 20 is formed only in the cellregion of the substrate 10. In the present embodiment, the secondphotoresist pattern 20 is positioned between gate patterns, so that apair of the gate electrode patterns is formed below both side portionsof the second photoresist pattern 20.

Referring to FIGS. 3A and 3B, the buffer layer 18 is partially etchedusing the second photoresist pattern as an etching mask, thus a lineshaped buffer pattern 18 a is formed on the polysilicon layer 16 in thecell region. Accordingly, a top surface of the polysilicon layer 16 ispartially exposed through the buffer pattern 18 a. An interval of thegate pattern may be controlled in accordance with a line width and aninterval of the buffer pattern 18 a. That is, when the line width of thebuffer pattern 18 a is reduced, the interval of a pair of the gatepatterns is also reduced since the gate pattern is formed below bothside portions of the buffer pattern 18 a. In addition, when the intervalof the buffer pattern 18 a is reduced, an interval among a gate patterngroup including a pair of the gate patterns formed below both sideportions of the buffer pattern 18 a is also reduced.

Referring to FIGS. 4A and 4B, a hard mask layer is formed on thepolysilicon layer 16 and the buffer pattern 18 a by a depositionprocess. The hard mask layer functions as an etching mask in an etchingprocess for patterning the polysilicon layer 16 into a gate electrode.Therefore, the hard mask layer comprises a material having an etchingselectivity with respect to both the buffer pattern 18 a and thepolysilicon layer 16. Examples of the hard mask layer include a siliconoxynitride layer, a silicon nitride layer, etc.

In the present embodiment, a thickness of the hard mask layer may besmaller than a critical dimension (CD) of a pattern formed by aphotolithography process. In addition, a thickness or characteristicdistribution of the hard mask layer is relatively small as compared withthe hard mask layer formed by the photolithography process, since thedeposition process is superior to the photolithography process inprocess stability.

A third photoresist layer is coated on the hard mask layer, and thethird photoresist layer in the cell region is removed and the thirdphotoresist layer in the peripheral region remains for masking theperipheral region, thereby forming a third photoresist pattern 21.

The hard mask layer is anisotropically etched, thus a spacer 22 isselectively formed along a sidewall of the buffer pattern 18 a. When theanisotropical etching process is completed, the spacer 22 is formed on asidewall of the buffer layer 18 a in the cell region and the hard masklayer 24 remains in the peripheral region since the peripheral region iscovered with the third photoresist pattern 21.

Referring to FIGS. 5A and 5B, the buffer pattern 18 a is selectivelyremoved through a dry or a wet etching process, thus the spacer 22separated form the buffer layer 18 a remains on the polysilicon layer 16in the cell region along a first direction. For example, the firstdirection may be in parallel with a direction of a line shaped activepattern. The hard mask layer 24 still remains since the buffer pattern18 a is not disposed in the peripheral region.

Referring to FIGS. 6A and 6B, a fourth photoresist film is coated on thespacer 22, the hard mask layer 24 and the polysilicon layer 16, and thenis patterned into a fourth photoresist pattern 30 by thephotolithography process. The photoresist pattern 30 in the cell regionis used as a hard mask for forming the spacer 22 into a cell gate, andthe photoresist pattern 30 in the peripheral region is used as a hardmask for forming the hard mask layer 24 into a peripheral gate.

The cell gate of the I-type SRAM is formed to be an independent patternseparated from each other just like islands perpendicular to the activepattern underlying the isolated independent pattern. Therefore, the lineshaped spacer 22 is partially etched into a plurality of independentlyseparated patterns perpendicular to the active region so as to patternthe spacer 22 into the hard mask for forming the cell gate.

Therefore, the fourth photoresist pattern 30 is formed in a seconddirection different from the first direction. In the present embodiment,the second direction is perpendicular to the first direction.Accordingly, the line shaped spacer 22 is partially exposed through thefourth photoresist pattern 30 in the cell region, and is to be etched ina subsequent process along the second direction. The fourth photoresistpattern 30 in the peripheral region is formed so as to form theperipheral gate in accordance with a design shape.

Referring to FIGS. 7A and 7B, the spacer 22 and the hard mask layer 24are partially etched using the fourth photoresist pattern as an etchingmask, so that the spacer 22 extending in the first direction is etchedaway in the second direction. Therefore, the spacer 22 is formed intothe island-like pattern in the cell region, thereby forming a cell gatehard mask pattern 22 a. The hard mask layer 24 in the peripheral regionis formed into a peripheral gate hard mask pattern 24 a. A line width ofthe cell gate hard mask pattern 22 a can be less than that of theperipheral gate hard mask pattern 24 a.

Accordingly, the cell gate hard mask pattern 22 a has a line widthsmaller than the CD of the photolithography process, and the peripheralgate hard mask pattern does not have a repeated shape but variousshapes. In addition, the cell gate hard mask pattern 22 a is formed notby the conventional photolithography process, but rather by thedeposition and anisotropic etching process, so that the above-mentionedline width variation and the line edge roughness are minimized.

Referring to FIGS. 8A and 8B, the polysilicon layer 16 is partiallyetched using the cell and peripheral gate hard mask patterns 22 a and 24a as an etching mask, so that a cell gate pattern 32 and a peripheralgate pattern 34 are formed at one time. Then, the cell gate andperipheral gate hard mask patterns 22 a and 24 a remaining on the cellgate pattern 32 and a peripheral gate pattern 34 are completely removed.

Embodiment 2

FIGS. 9A through 11 are plan views and cross sectional views showingprocessing steps of a method of forming a pattern of an I-type staticrandom access memory (SRAM) device according to a second embodiment ofthe present invention. Throughout FIGS. 9A through 10B, each capitalletter A designates a plan view illustrating the I-type SRAM device, andeach capital letter B designates a cross sectional view taken along theline I-I′ of the corresponding figure designated by the capital letterA.

The present second embodiment of the present invention is the same asthe first embodiment of the present invention except that a separationlayer is added between the gate electrode layer and the buffer layer.

Referring to FIGS. 9A and 9B, a semiconductor substrate 10 including acell region and a peripheral region is provided, and a field region andan active region are defined by the same process as described in thefirst embodiment with reference to FIG. 1. Therefore, a unit memorydevice is positioned in the cell region, and a driving circuit fordriving the unit memory device is positioned in the peripheral region.The active region is formed into a line shaped pattern on the substrate10.

Then, a gate oxide layer 14 is formed on the substrate 10 including theline shaped active pattern to a thickness of about 10 Å to about 300 Å,and a first polysilicon layer 16 for forming a gate electrode is formedon the gate oxide layer 14. A metal silicide layer (not shown) may befurther formed on the polysilicon layer 16.

A separation layer 40 is formed on the first polysilicon layer 16 forseparating the first polysiliocn layer 16 and a buffer layer 42 formedthereon in a subsequent process. The separation layer 40 comprises amaterial having an etching selectivity with respect to the firstpolysilicon layer 16. Example of the separation layer 16 includessilicon oxide.

A second polysilicon layer is formed on the separation layer 40 as thebuffer layer 42. That is, the buffer layer 42 has the same material asthe gate electrode under the buffer layer 42, thus the separation layer40 is used between the first and second polysilicon layers 16 and 40.

A photoresist film is coated on the second polysilicon layer 42. Thephotoresist film in the cell region is selectively removed, and thephotoresist film in the peripheral region is completely removed, thusonly the photoresist film in the cell region is formed into photoresistpattern 44. In the present embodiment, the photoresist pattern 44 isformed between gate patterns, so that a pair of the gate electrodepatterns is positioned below both side portions of the photoresistpattern 44.

Referring to FIGS. 10A and 10B, a cell gate hard mask pattern 22 a and aperipheral gate hard mask pattern 24 a are formed on the separatinglayer 40 at a time by the same process as the first embodiment describedwith reference to FIGS. 3A through 7B.

Referring to FIG. 11, the separating layer 40 and the first polysiliconlayer 16 are sequentially etched using the cell and peripheral hard maskpatterns 22 a and 24 a as an etching mask, thus a cell gate pattern 52,a peripheral pattern 54 and a separation layer pattern 40 a are formed.The remaining cell and peripheral hard mask patterns 22 a and 24 a areremoved from the cell gate pattern 52, the peripheral pattern 54 and theseparation layer pattern 40 a. The separating layer pattern 40 a mayremain on the peripheral pattern 54 or be removed from the peripheralpattern 54.

Embodiment 3

FIGS. 12A through 20B are plan views and cross sectional views showingprocessing steps of a method of forming a gate of an I-type staticrandom access memory (SRAM) device according to a third embodiment ofthe present invention. Throughout FIGS. 12A through 20B, each capitalletter A designates a plan view illustrating the I-type SRAM device, andeach capital letter B designates a cross sectional view taken along theline I-I′ of the corresponding figure designated by the capital letterA.

Referring to FIGS. 12A and 12B, a semiconductor substrate 10 including acell region and a peripheral region is provided, and a field region andan active region are defined by the same process as described in thesecond embodiment with reference to FIGS. 9A and 9B. Therefore, a unitmemory device is positioned in the cell region, and a driving circuitfor driving the unit memory device is positioned in the peripheralregion. The active region is formed into a line shaped pattern on thesubstrate 10.

Then, a gate oxide layer 14 is formed on the substrate 10 including theline shaped active pattern to a thickness of about 10 Å to about 300 Å,and a first polysilicon layer 16 for forming a gate electrode is formedon the gate oxide layer 14. A metal silicide layer (not shown) may befurther formed on the polysilicon layer 16. A separation layer 40 isformed on the first polysilicon layer 16 for separating the firstpolysilicon layer 16 and a buffer layer 42 formed thereon in asubsequent process. The separation layer 40 comprises a material havingan etching selectivity with respect to the first polysilicon layer 16.An example of the separation layer 16 includes silicon oxide.

A second polysilicon layer is formed on the separation layer 40 as thebuffer layer 42. The buffer layer 42 has the same material as the gateelectrode under the buffer layer 42, thus the separation layer 40 isnecessarily required between the first and second polysilicon layers 16and 40. A thickness of the cell hard mask pattern for patterning thefirst polysilicon layer 16 is determined in accordance with a thicknessof the second polysilicon layer 42.

A first photoresist film (not shown) is coated on the second polysiliconlayer 42. The first photoresist film in the cell region is selectivelyremoved, and the first photoresist film in the peripheral region iscompletely removed, thus only the first photoresist film in the cellregion is formed into a first photoresist pattern. In the presentembodiment, the first photoresist pattern is formed between gatepatterns, so that a pair of the gate electrode patterns is positionedbelow both side portions of the photoresist pattern.

Then, the second polysilicon layer is selectively etched using the firstphotoresist pattern as an etching mask by the same process as the secondembodiment described with reference to FIGS. 9A and 9B, so that a secondpolysilicon pattern 42 a having a line shape is formed on the separationlayer 40 in the cell region, and a top surface of the separation layer40 is partially exposed through the second polysilicon pattern 42 a. Aninterval of a gate pattern that is to be formed in a subsequent processmay be controlled in accordance with a line width and an interval of thesecond polysilicon pattern 42 a. That is, when the line width of thesecond polysilicon pattern 42 a is reduced, the interval of a pair ofthe gate patterns is also reduced since the gate pattern is formed belowboth side portions of the second polysilicon pattern 42 a. In addition,when the interval of the second polysilicon pattern 42 a is reduced, aninterval among a gate pattern group including a pair of the gatepatterns formed below both side portions of the second polysiliconpattern 42 a is also reduced.

Referring to FIGS. 13A and 13B, a space layer such as a siliconoxynitride layer or a silicon nitride layer is formed on the separationlayer 40 and the second polysilicon pattern 42 a for forming a spacer 60by a deposition process. The spacer layer comprises a material having anetching selectivity with respect to the second polysilicon pattern 42 a.

In the present embodiment, a thickness of the spacer layer may be formedto be less than the CD of a pattern formed by the conventionalphotolithography process, and a thickness or a characteristicdistribution of the spacer layer is relatively small as compared withthe spacer layer formed by the photolithography process, since thedeposition process is superior to the photolithography process inprocess stability.

Then, the spacer layer is anisotropically removed by, for example, anetching process, and a spacer 60 that comprises, for example, nitride,is selectively formed along a sidewall of the second polysilicon pattern42 a. That is, when the anisotropical etching process is completed, aremaining portion of the spacer layer except for the spacer 60 along thesidewall of the second polysilicon pattern 42 a is removed in the cellregion and the peripheral region. Therefore, the top surface of theseparating layer 40 is partially exposed in the cell region, and iscompletely exposed in the peripheral region. The spacer 60 is used as ahard mask pattern for forming a cell gate in a subsequent process.

Referring to FIGS. 14A and 14B, the second polysilicon layer 42 a isselectively removed from the separating layer 40 by a dry or a wetetching process, thus only a plurality of the spacers 60 remains on theseparating layer 40 at a predetermined interval in the cell region alonga first direction, and no spacer remains on the separating layer 40 inthe peripheral region. That is, the top surface of the separating layer40 is partially exposed in the cell region, and is completely exposed inthe peripheral region. For example, the first direction may be inparallel with a direction of a line shaped active pattern.

Referring to FIGS. 15A and 15B, a hard mask layer 62 is formed on theseparating layer 40 on which the spacer is formed having a profilerepresenting the spacer 60. That is, the hard mask layer 62corresponding to the spacer 60 is protruded upwardly as compared withthe hard mask layer 62 corresponding to the separating layer 40 in theperipheral region.

The hard mask layer 62 comprises the same material as the spacer 60 or amaterial having an etching selectivity with respect to the spacer 60.The hard mask layer 62 and the spacer 60 can have the same etchingcharacteristics since the hard mask layer 62 and the spacer 60 are usedas a peripheral hard mask pattern and a cell hard mask pattern,respectively, in a subsequent process. Examples of the hard mask layer62 include a silicon oxynitride layer, a silicon nitride layer, etc.

Referring to FIGS. 16A and 16B, a second photoresist film is coated onthe hard mask layer 62, and then is partially removed by thephotolithography process to be formed into a second photoresist pattern64 in a second direction different from the first direction. Forexample, the second direction is perpendicular to the first direction.The second photoresist film in the cell region is partially removed,thus a hard mask pattern for forming the cell gate is formed in the cellregion. The second photoresist film in the peripheral region is notremoved, thus the hard mask layer 62 is completely covered with thesecond photoresist film in the peripheral region. In detail, the hardmask layer 62 is partially exposed through the second photoresistpattern 64 in the cell region, and is to be etched in a subsequentprocess along the second direction.

The cell gate of the I-type SRAM is formed to be an independent patternseparated from each other just like islands perpendicular to a lineshaped active pattern underlying the island-like pattern. Theindependently separated island-like pattern may be formed by partiallyetching a cell gate electrode layer using the hard mask pattern as anetching mask. In the present embodiment, the hard mask layer is etchedalong the second direction perpendicular to the first direction.

Referring to FIGS. 17 a and 17 b, the hard mask layer 62 and the spacer60 are etched using the second photoresist pattern 64 as an etching maskin the second direction until the separating layer 40 is partiallyexposed through the second photoresist pattern 64. Accordingly, the hardmask layer 62 and the spacer 60 extending in the first direction arepartially trimmed away in the second direction in the cell region of thesubstrate. Therefore, the spacer 60 is formed into the island-likepattern in the cell region. The second photoresist pattern 64 remainingon the hard mask layer 62 is removed by a conventional ashing andstripping process.

Referring to FIGS. 18A and 18B, a third photoresist film is coated onthe trimmed hard mask layer 62, and is partially removed by aphotolithography process thereby forming a third photoresist pattern 66.That is, while the third photoresist film in the cell region iscompletely removed, and the hard mask layer is fully exposed, the thirdphotoresist film in the peripheral region is partially removed, and thehard mask layer is partially exposed through the third photoresistpattern 66 in the peripheral region. The third photoresist pattern 66 isused as a mask pattern for forming a peripheral gate in the peripheralregion of the substrate.

Referring to FIGS. 19A and 19B, the hard mask layer 62 a isanisotropically etched using the third photoresist pattern 66 as anetching mask, so that a hard mask pattern 70 and 72 is formed on thecell region and peripheral region, respectively. Then, the thirdphotoresist pattern 66 is removed by a conventional ashing and strippingprocess.

In detail, the hard mask pattern 62 a in the cell region is completelyetched away, thus the spacer 60 and the separating layer 40 is exposed.In the present embodiment, the spacer 60 that has been already formedinto the independently separated island-like pattern by a formertrimming process is used as a hard mask pattern 70 for forming a cellgate electrode. The hard mask pattern 62 a in the peripheral region isused as a peripheral hard mask pattern 72 for forming a peripheral gate.In the present embodiment, the cell gate hard mask pattern 70 has asmaller line width than the peripheral hard mask pattern 72.

Referring to FIGS. 20A and 20B, the separating layer 40 and the firstpolysilicon layer 16 are partially etched using the cell and peripheralhard mask patterns 70 and 72 as an etching mask, thereby forming thecell and peripheral gate patterns 74 and 76. Then, the cell andperipheral gate hard mask patterns 70 and 72 remaining on a patternedseparating layer 40 are completely removed. The patterned separatinglayer may remain on a patterned first polysilicon layer, or becompletely removed from the patterned first polysilicon layer.

The present embodiment of the invention may be modified without usingthe separation layer in a similar way described in the first embodimentof the invention, as would be known to one of the ordinary skill in theart. The gate electrode layer and the buffer layer may comprisedifferent materials, such that the separating layer is not required.Accordingly, the modified embodiment is the same as the third embodimentof the present invention except that no separation layer is providedbetween the first and second polysilicon layers since the first andsecond polysilicon layers comprise the same material.

Hereinafter, the modified embodiment is described in detail.

The semiconductor substrate including a cell region and a peripheralregion is provided, and a field region and an active region are definedas described with reference to FIGS. 12A and 12B. Therefore, a unitmemory device is positioned in the cell region, and a driving circuitfor driving the unit memory device is positioned in the peripheralregion. The active region is formed into a line shaped pattern on thesubstrate.

Then, a gate oxide layer is formed on the substrate including the lineshaped active pattern to a thickness of about 10 Å to about 300 Å, and apolysilicon layer for forming a gate electrode is formed on the gateoxide layer. A metal silicide layer may be further formed on thepolysilicon layer.

A buffer layer is formed on the polysilicon layer. The buffer layercomprises a material having an etching selectivity with respect to thepolysilicon layer such as silicon oxide. According to the same processdescribed above, the cell and peripheral gate electrode patterns areformed on the substrate.

According to the embodiments of the present invention, the gate patternhas a smaller line width in the cell region than in the peripheralregion. The gate pattern is also formed to have a line width smallerthan the CD of the photolithography process by using the depositionprocess. In addition, since the gate pattern is formed without using thephotolithography process, a recent expensive short wave exposingapparatus and a photoresist material related thereto are not required,so that manufacturing cost for the high minute gate pattern is reduced.Furthermore, since the gate pattern is formed by the etching processusing a hard mask pattern as an etching mask, the above-mentionedproblems due to the photolithography process such as the line widthvariation and the edge roughness may be minimized. Although the aboveexemplary embodiments discuss the cell gate and the peripheral gate ofthe I-type SRAM device, an active pattern or a metal wiring could alsobe formed by the same method discussed above, as would be known to oneof an ordinary skill in the art.

In particular, when the line width of the gate pattern is less than orequal to about 70 um, the cost for performing the photolithographyprocess is remarkably increased due to the very high price thereof.Therefore, the present invention considerably reduces the manufacturingcost of the semiconductor device by patterning the fine gate patternwithout using the photolithography process as well as minimizing theline width variation and the edge roughness.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A method of forming a pattern of a semiconductor device, comprising:providing a semiconductor substrate on which an object layer to bepatterned is formed, the substrate being divided into a cell region anda peripheral region; forming a buffer layer on the object layer;partially etching the buffer layer by a photolithography process suchthat the buffer layer in the cell region of the substrate is formed intoa buffer pattern, and the buffer layer in the peripheral region of thesubstrate is removed; forming a hard mask layer on the buffer pattern inthe cell region and the object layer in the peripheral region;selectively etching the hard mask layer only in the cell region of thesubstrate anisotropically, so that a spacer is formed along a sidewallof the buffer pattern in the cell region, and the hard mask layer stillremains on the object layer in the peripheral region of the substrate;removing the buffer pattern from the object layer, so that only thespacer remains on the object layer along a first direction; at leastpartially removing the spacer in a second direction different from thefirst direction and the hard mask layer, so that the spacer is separatedalong the second direction, thereby forming a cell hard mask pattern inthe cell region and a peripheral hard mask pattern is formed in theperipheral region; and etching the object layer using the cell hard maskpattern and the peripheral hard mask pattern as an etching mask.
 2. Themethod of claim 1, wherein the buffer layer comprises a material havingan etching selectivity with respect to the hard mask layer.
 3. Themethod of claim 1, wherein the hard mask layer comprises a materialhaving an etching selectivity with respect to both the object layer andthe buffer layer.
 4. The method of claim 1, the buffer layer includes atleast one of a silicon oxide layer and a polysilicon layer.
 5. Themethod of claim 1, further comprising forming a separation layer betweenthe object layer and the buffer layer for separating the object layerfrom the buffer layer, the separation layer comprising a material havinga high etching selectivity with respect to the object layer when theobject layer comprises the same material as the buffer layer.
 6. Themethod of claim 1, wherein the hard mask layer comprises at least one ofa silicon oxynitride layer and a silicon oxide layer.
 7. The method ofclaim 1, wherein the object layer includes a gate electrode layer, asilicon substrate in a field region or a metal layer for forming a metalwiring.
 8. The method of claim 1, wherein a width of the spacer is lessthan a critical dimension (CD) of a photolithography process.
 9. Themethod of claim 1, wherein a line width of the peripheral hard maskpattern is greater than that of the cell hard mask pattern.
 10. A methodof forming a pattern of a semiconductor device, comprising: providing asemiconductor substrate on which an object layer to be patterned isformed, the substrate being divided into a cell region and a peripheralregion; forming a buffer layer on the object layer; at least partiallyetching the buffer layer from the object layer by a photolithographyprocess such that the buffer layer in the cell region of the substrateis formed into a buffer pattern, and the buffer layer in the peripheralregion of the substrate is removed; forming a spacer along a sidewall ofthe buffer pattern; removing the buffer pattern from the object layer,so that only the spacer remains on the object layer along a firstdirection; forming a hard mask layer on the object layer including thespacer extending along the first direction; at least partially removingthe hard mask layer and the spacer in a second direction different fromthe first direction in the cell region of the substrate, so that thespacer and the hard mask layer on the spacer are separated from eachother along the second direction in the cell region; at least partiallyremoving the hard mask layer such that the hard mask layer on the spaceris removed in the cell region of the substrate and the hard mask layeron the object layer is at least partially removed in the peripheralregion of the substrate, thereby forming a cell hard mask pattern in thecell region of the substrate and a peripheral hard mask pattern in theperipheral region of the substrate; and at least partially etching theobject layer using the cell hard mask pattern and the peripheral hardmask pattern as an etching mask.
 11. The method of claim 10, wherein thebuffer layer comprises a material having a high etching selectivity withrespect to the hard mask layer.
 12. The method of claim 10, furthercomprising, in case that the object layer comprises the same material asthe buffer layer, forming a separation layer between the object layerand the buffer layer for separating the object layer from the bufferlayer, the separation layer comprising a material having a high etchingselectivity with respect to the object layer.
 13. The method of claim10, wherein the spacer and the hard mask layer comprise a materialhaving a high etching selectivity with respect to the object layer andthe buffer layer.
 14. The method of claim 10, wherein the hard masklayer is the same material as the spacer.
 15. The method of claim 10,wherein the hard mask layer comprises at least one of a siliconoxynitride layer and a silicon oxide layer.
 16. The method of claim 10,wherein the object layer includes at least one of a gate electrodelayer, a silicon substrate in a field region and a metal layer forforming a metal wiring.
 17. A method of forming a gate in asemiconductor device, comprising: forming a gate oxide layer and a gateelectrode layer on a substrate, the substrate being divided into a cellregion and a peripheral region; forming a buffer layer on the gateelectrode layer; at least partially etching the buffer layer from thegate electrode layer by a photolithography process such that the bufferlayer in the cell region of the substrate is formed into a bufferpattern, and the buffer layer in the peripheral region of the substrateis removed; forming a hard mask layer on the buffer pattern in the cellregion of the substrate and the gate electrode layer in the peripheralregion of the substrate; selectively etching the hard mask layer only inthe cell region of the substrate anisotropically, so that a spacer isformed along a sidewall of the buffer pattern in the cell region, andthe hard mask layer still remains on the gate electrode layer in theperipheral region of the substrate; removing the buffer pattern from thegate electrode layer, so that only the spacer remains on the gateelectrode layer along a first direction; at least partially removing thespacer in a second direction different from the first direction and thehard mask layer, so that the spacer is separated the second direction,thereby forming a cell hard mask pattern in the cell region and aperipheral hard mask pattern in the peripheral region; and at leastpartially etching the gate electrode layer using the cell hard maskpattern and the peripheral hard mask pattern as an etching mask.
 18. Themethod of claim 17, wherein the gate electrode layer comprisespolysilicon.
 19. The method of claim 18, wherein the buffer layerincludes at least one of a silicon oixde layer and a polysiliocn layer.20. The method of claim 19, further comprising, in case that the bufferlayer includes the polysilicon layer, forming a separation layer betweenthe gate electrode layer and the buffer layer for separating the gateelectrode layer from the buffer layer, the separation layer comprising amaterial having a high etching selectivity with respect to polysilicon.21. The method of claim 17, wherein the hard mask layer comprises atleast one of a silicon oxynitride layer and a silicon oxide layer.
 22. Amethod of forming a gate in a semiconductor device, comprising: forminga gate oxide layer and a gate conductive layer on a substrate that isdivided into a cell region and a peripheral region; forming a bufferlayer on the gate conductive layer; at least partially etching thebuffer layer from the gate conductive layer by a photolithographyprocess such that the buffer layer in the cell region of the substrateis formed into a buffer pattern, and the buffer layer in the peripheralregion of the substrate is removed; forming a spacer along a sidewall ofthe buffer pattern; removing the buffer pattern from the gate conductivelayer, so that only the spacer remains on the gate conductive layeralong a first direction; forming a hard mask layer on the gateconductive layer including the spacer extending along the firstdirection; at least partially etching the hard mask layer and the spacerin a second direction different from the first direction in the cellregion of the substrate, so that the spacer and the hard mask layer onthe spacer are separated from each other along the second direction inthe cell region; at least partially etching the hard mask layer suchthat the hard mask layer on the spacer is removed in the cell region ofthe substrate and the hard mask layer on the gate conductive layer is atleast partially removed in the peripheral region of the substrate,thereby forming a cell hard mask pattern in the cell region of thesubstrate and a peripheral hard mask pattern in the peripheral region ofthe substrate; and at least partially etching the gate conductive layerusing the cell hard mask pattern and the peripheral hard mask pattern asan etching mask.
 23. The method of claim 22, wherein the gate electrodelayer comprises polysilicon.
 24. The method of claim 23, wherein thebuffer layer includes at least one of a silicon oxide layer and apolysilicon layer.
 25. The method of claim 24, further comprising, incase that the buffer layer comprises polysilicon, forming a separationlayer between the gate conductive layer and the buffer layer forseparating the gate conductive layer from the buffer layer, theseparation layer comprising a material having an etching selectivitywith respect to the polysilicon.
 26. The method of claim 22, wherein thehard mask layer includes at least one of a silicon oxynitride layer anda silicon oxide layer.